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ATmega128
Table 98. Input Channel and Gain Selections (Continued)
Single Ended
Positive Differential
Negative Differential
MUX4..0
11101
11110
Input
1.23V (V BG )
Input
ADC5
N/A
Input
ADC2
Gain
1x
ADC Control and
11111
Note:
0V (GND)
1. Can be used for offset calibration.
Status Register A –
Bit
7
6
5
4
3
2
1
0
ADCSRA
Read/ W rite
Initial Value
ADEN
R/ W
0
ADSC
R/ W
0
ADFR
R/ W
0
ADIF
R/ W
0
ADIE
R/ W
0
ADPS2
R/ W
0
ADPS1
R/ W
0
ADPS0
R/ W
0
ADCSRA
? Bit 7 – ADEN: ADC Enable
W riting this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the
ADC off while a conversion is in progress, will terminate this conversion.
? Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode,
write this bit to one to start the first conversion. The first conversion after ADSC has been written
after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,
will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa-
tion of the ADC.
ADSC will read as one as long as a conversion is in progress. W hen the conversion is complete,
it returns to zero. W riting zero to this bit has no effect.
? Bit 5 – ADFR: ADC Free Running Select
W hen this bit is written to one, the ADC operates in Free Running mode. In this mode, the ADC
samples and updates the data registers continuously. W riting zero to this bit will terminate Free
Running mode.
? Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the data registers are updated. The ADC
Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is
cleared by hardware when executing the corresponding interrupt handling vector. Alternatively,
ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on
ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions
are used.
? Bit 3 – ADIE: ADC Interrupt Enable
W hen this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter-
rupt is activated.
? Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the XTAL frequency and the input clock to the
ADC.
244
2467X–AVR–06/11
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